From 5659a25b5c6b340656a0809d3d5a6d2c11bf528a Mon Sep 17 00:00:00 2001
From: Lucian Mogosanu <lucian.mogosanu@gmail.com>
Date: Wed, 24 Dec 2014 01:26:42 +0200
Subject: [PATCH] Z80: ISA: Add 8-bit IX and IY regs

I'm not sure whether this is the best approach, but I'm choosing it for
now. I'm envisioning a massive refactoring sometime in the future, of
the *entire* decoding machine, not only this particular part. I'll
probably need to wrap all this in yet another State monad.
---
 src/Z80/ISA.hs |   24 ++++++++++++++----------
 1 file changed, 14 insertions(+), 10 deletions(-)

diff --git a/src/Z80/ISA.hs b/src/Z80/ISA.hs
index fbb98e6..015ae53 100644
--- a/src/Z80/ISA.hs
+++ b/src/Z80/ISA.hs
@@ -5,16 +5,16 @@ import Data.Word
 import Data.Int
 
 -- regs, as seen by the programmer
-data Reg = B | C | D | E | H | L | PHL | A deriving Eq
+data Reg = B | C | D | E | H | L | PHL | A | IXH | IXL | IYH | IYL deriving Eq
 
 -- reg pairs specified in the z80 manual
-data BC = BC
-data DE = DE
-data HL = HL
-data SP = SP
-data AF = AF
-data IX = IX
-data IY = IY
+data BC = BC deriving Eq
+data DE = DE deriving Eq
+data HL = HL deriving Eq
+data SP = SP deriving Eq
+data AF = AF deriving Eq
+data IX = IX deriving Eq
+data IY = IY deriving Eq
 
 -- sets of reg pairs used in the z80 manual
 data RegPair a b c d = R1 a | R2 b | R3 c | R4 d deriving Eq
@@ -227,6 +227,10 @@ instance Show Reg where
     H -> "h"
     L -> "l"
     PHL -> "(hl)"
+    IXH -> "ixh"
+    IXL -> "ixl"
+    IYH -> "iyh"
+    IYL -> "iyl"
 
 instance Show BC where show BC = "bc"
 instance Show DE where show DE = "de"
@@ -429,9 +433,9 @@ instance Show Instruction where
     OUT_PC_R  r -> "out (c)," ++ show r
     OUT_PC_Zero -> "out (c),0"
     OUTI        -> "outi"
-    OUTIR       -> "outir"
+    OUTIR       -> "otir"
     OUTD        -> "outd"
-    OUTDR       -> "outdr"
+    OUTDR       -> "otdr"
     -- illegal
     IllegalInstruction  s -> "db " ++ s
 
-- 
1.7.10.4