Add initial source files

diff --git a/src/Data/Z80/CPU.hs b/src/Data/Z80/CPU.hs
new file mode 100644 (file)
index 0000000..ca13a47
--- /dev/null
+++ b/src/Data/Z80/CPU.hs
@@ -0,0 +1,43 @@
+module Data.Z80.CPU where
+
+import Data.Word
+
+data CPU = CPU
+  { af  :: Word16
+  , bc  :: Word16
+  , de  :: Word16
+  , hl  :: Word16
+  , af' :: Word16
+  , bc' :: Word16
+  , de' :: Word16
+  , hl' :: Word16
+  , i   :: Word8
+  , r   :: Word8
+  , ix  :: Word16
+  , iy  :: Word16
+  , sp  :: Word16
+  , pc  :: Word16
+  } deriving (Show, Eq)
+
+-- not really into lenses so we're using those for now
+setAF, setBC, setDE, setHL :: CPU -> Word16 -> CPU
+setAF cpu w = cpu { af = w }
+setBC cpu w = cpu { bc = w }
+setDE cpu w = cpu { de = w }
+setHL cpu w = cpu { hl = w }
+
+setAF', setBC', setDE', setHL' :: CPU -> Word16 -> CPU
+setAF' cpu w = cpu { af' = w }
+setBC' cpu w = cpu { bc' = w }
+setDE' cpu w = cpu { de' = w }
+setHL' cpu w = cpu { hl' = w }
+
+setIX, setIY, setSP, setPC :: CPU -> Word16 -> CPU
+setIX cpu w = cpu { ix = w }
+setIY cpu w = cpu { iy = w }
+setSP cpu w = cpu { sp = w }
+setPC cpu w = cpu { pc = w }
+
+setI, setR :: CPU -> Word8 -> CPU
+setI cpu b = cpu { i = b }
+setR cpu b = cpu { r = b }

diff --git a/src/Data/Z80/ISA.hs b/src/Data/Z80/ISA.hs
new file mode 100644 (file)
index 0000000..7f77186
--- /dev/null
+++ b/src/Data/Z80/ISA.hs
@@ -0,0 +1,60 @@
+module Data.Z80.ISA where
+
+import Data.Word
+import Data.Int
+
+--data Reg = AF | BC | DE | HL | AF' | BC' | DE' | HL'
+--         | I | R | IX | IY | SP | PC deriving (Show, Eq)
+
+-- regs, as seen by the programmer
+data Reg = A | B | C | D | E | H | L deriving (Show, Eq)
+
+data RegPair = BC | DE | HL | SP deriving (Show, Eq)
+
+-- XXX Should 
+data Instruction =
+  -- 8-bit load group
+    LD_R_R'     Reg Reg
+  | LD_R_N      Reg Word8
+  | LD_R_PHL    Reg
+  | LD_R_PIX    Reg Int8
+  | LD_R_PIY    Reg Int8
+  | LD_PHL_R    Reg
+  | LD_PIX_R    Int8 Reg
+  | LD_PIY_R    Int8 Reg
+  | LD_PHL_N    Word8
+  | LD_PIX_N    Int8 Word8
+  | LD_PIY_N    Int8 Word8
+  | LD_A_PBC
+  | LD_A_PDE
+  | LD_A_PNN    Word16
+  | LD_PBC_A
+  | LD_PDE_A
+  | LD_PNN_A    Word16
+  | LD_A_I
+  | LD_A_R
+  | LD_I_A
+  | LD_R_A
+  -- 16-bit load group
+  | LD_DD_NN  RegPair Word16
+  | LD_IX_NN  Word16
+  | LD_IY_NN  Word16
+  | LD_HL_PNN  Word16
+  | LD_DD_PNN  RegPair Word16
+  | LD_IX_PNN Word16
+  | LD_IY_PNN Word16
+  | LD_PNN_HL Word16
+  | LD_PNN_DD Word16 RegPair
+  | LD_PNN_IX Word16
+  | LD_PNN_IY Word16
+  | LD_SP_HL
+  | LD_SP_IX
+  | LD_SP_IY
+  | PUSH_QQ RegPair
+  | PUSH_IX
+  | PUSH_IY
+  | POP_QQ RegPair
+  | POP_IX
+  | POP_IY
+  -- TODO: exchange, block transfer and search group
+  -- TODO: others

diff --git a/src/Data/Z80/Memory.hs b/src/Data/Z80/Memory.hs
new file mode 100644 (file)
index 0000000..075a50d
--- /dev/null
+++ b/src/Data/Z80/Memory.hs
@@ -0,0 +1,9 @@
+module Data.Z80.Memory where
+
+import Data.Array
+import Data.Word
+
+type Memory = Array Int Word16
+
+romMem :: Memory
+romMem = listArray (0x0000, 0x3fff) $ repeat 0